Tristate buffers are typically used for buffering clock signals in integrated electronic devices. Tristate buffers can be switched into a high impedance state in order to hold the clock in the electronic device or to allow another buffer to take over control of a clock line. If the clock is switched synchronously, then the clock can be only switched at an appropriate moments with a safety margin from the falling or rising edges of the clock signal. For asynchronous systems, a tristate signal effectively switching the buffered clock signal off can occur at any time within a clock period. If the tristate buffer is switched off or on coincidentally with an edge of the clock signal, a glitch can occur. A glitch can still trigger some of the clocked components coupled to the tristate buffer output. Others components may not be clocked correctly. Glitches thus typically risk malfunctions and should be avoided.